Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device in which various parameters for a minimum margin of data transfer are prescribed according to a specification.
Generally, in a semiconductor memory device including a Double Data Rate Synchronous DRAM (DDR SDRAM), various parameters are prescribed according to a specification. Examples of the parameters include ‘tAC’, ‘tDQSCK’, ‘tDQSS’, and the like. ‘tAC’ is a parameter which relates to a clock signal and a data, and ‘tDQSCK’ is a parameter which relates to the clock signal and a data strobe signal. ‘tDQSS’ is a parameter which relates to the data and the data strobe signal. A test operation is performed on the semiconductor memory device before mass-producing the semiconductor memory device in order to determine whether the parameters are properly guaranteed.
As an example, for illustration purposes, ‘tAC’ is described in detail. As mentioned above, ‘tAC’ is the parameter which relates to the clock signal and the data. ‘tAC’ is defined as a minimum value and a maximum value where the data is desired to be positioned with respect to a rising edge of the clock signal. In other words, the data transferred through different transfer paths have different transfer timings due to various factors; however, despite occurrence of such a data skew in comparison with the clock signal, it is possible for the semiconductor memory device to perform a desired operation. Accordingly, ‘tAC’ defines a range of a permissible the data skew where the semiconductor memory device can perform normal operations.
For instance, in performing a test which relates to ‘tAC’ for the semiconductor memory device which outputs 16 pieces of data, 16 probe pins may be allocated in a test equipment and a test operation may be sequentially performed on each data output terminal through a respective probe pin. During the test operation, the test equipment detects ‘tAC’ of each subsequent data output terminal after detecting ‘tAC’ corresponding to a first data output terminal and detects ‘tAC’ of each of the 16 data output terminals and transfer the detection result to a test operator. Based on the detection result, the test operator adjusts an output timing of the latest output data.
Meanwhile, time for testing a semiconductor memory device is an important factor that determines the cost of the semiconductor memory device. Therefore, extensive efforts have been made to reduce the test time. One way to reduce the test time has been to reduce the number of probe pins allocated to a semiconductor memory device. Reduction in the number of probe pins often results in an increase in the number of semiconductor memory devices that the test equipment can simultaneously test. Thus, the test time for each semiconductor memory device can be reduced in testing a number of the semiconductor memory devices.
However, in performing the test operation for determining ‘tAC’ for a semiconductor memory device, it may be difficult to reduce the number of allocated probe pins since the test operation is typically performed on all of the data output terminals. While reduction in the number of allocated probe pins may be achieved by testing representative data output terminals, ‘tAC’ of the remaining data output terminals is not guaranteed. Accordingly, semiconductor memory devices may not operate reliably.